The successive approximation register analog-to-digital converter (hereafter referred to as “SAR ADC”) converts an analog input signal to an n-bit digital output signal. A system LSI such as a communication receiver unit has a differential type SAR ADC, and the above SAR ADC converts the polarity and the differential voltage of a differential analog input signal to a digital output signal. Then, an incorporated digital processing circuit performs desired processing, such as demodulation processing and decoding processing, to the digital output signal.
The above successive approximation register analog-to-digital converter (SAR ADC) includes a charge redistribution digital-to-analog converter (hereafter referred to as “charge redistribution DAC” or “CDAC”) for making a sampling voltage successively change after sampling the differential analog input signal according to a successive comparison result, a comparator for comparing the differential analog output signal, and a control circuit for supplying control digital signals to a digital-to-analog converter according to the comparison result by the comparator.
The following patent documents 1-4 disclose such converters.
Patent document 1 is the official gazette of the Japanese Unexamined Patent Publication No. 2007-142863.
Patent document 2 is the official gazette of the Japanese Unexamined Patent Publication No. 2006-503495.
Patent document 3 is the official gazette of the Japanese Unexamined Patent Publication No. 2003-152541.
Patent document 4 is the official gazette of the Japanese Unexamined Patent Publication No. Hei-6-164399.
In the SAR ADC described in the patent document 1 etc., in case of n bits, the operating speed to charge/discharge a capacitor is n times as high as a sampling frequency, or more. Further, power consumption by a charge/discharge current becomes greater as the speed becomes higher or the resolution becomes higher, and an occupation area by a capacitor inside the LSI is increased.
Further, accompanying charge transfer, the performance of the analog-to-digital converter in which high speed and high accuracy is required becomes deteriorated.